Non-volatile memory systems may be confined to packaging size requirements or specifications. In order to achieve an increased amount of storage capacity while adhering to these size requirements or specifications, a certain die layout identifying a number of dies, die capacities, and memory types for the dies may be chosen. Some die layouts may be incompatible with an existing initialization process or addressing scheme. Additionally, the chosen die layout may provide degraded endurance if implemented with existing storage management architectures. As such, it may be desirable to establish an addressing scheme, a wear leveling scheme, and/or an initialization process for the chosen die layout, particularly ones that may be compatible with the system's existing read-only memory (ROM) architecture.
Overview
Embodiments of the present invention are defined by the claims, and nothing this section should be taken as a limitation on those claims.
In one embodiment, a non-volatile memory system may include non-volatile memory comprising a plurality of physically present memory dies configured in a plurality of chip enable groups, where a chip enable group of the plurality of chip enable groups comprises a number of physically present memory dies that is less than a maximum number of memory dies allowed to be uniquely identified under a die selection scheme. The non-volatile memory system may also include a controller in communication with the non-volatile memory. The controller may be configured to select the plurality of physically present memory dies for communication according to the die selection scheme, and upon completing an initialization process, maintain an address mapping that maps addresses to storage locations of the non-volatile memory according to a virtual die layout that identifies the chip enable group as comprising the maximum number of memory dies.
In a second embodiment, a method of performing an initialization process of a non-volatile memory system comprising non-volatile memory, where the non-volatile memory comprises a plurality of physically present memory dies, may include: receiving, with a controller of the non-volatile memory system, an initialization command from a host system; in response to receiving the initialization command, initializing, with a read-only memory (ROM) module of the controller, an initial set of the physically present memory dies, wherein a number of physically present memory dies of the first set is less than a total number of the physically present memory dies; retrieving, with a random access memory (RAM) module of the controller, firmware stored in the non-volatile memory; and in response to retrieving the firmware, initializing, with the RAM module, a remaining set of the physically present memory dies.
In a third embodiment, a non-volatile memory system may include non-volatile memory comprising a plurality of memory dies, wherein each memory die of the plurality of memory dies has an associated capacity. The non-volatile memory system may also include a controller configured to perform write operations across the plurality of memory dies according to a wear leveling scheme that is based on capacity ratios associated with the plurality of memory dies. Each capacity ratio comprises a ratio of a capacity of an associated one of the plurality of memory dies to a largest capacity among the plurality of memory dies. In addition, among the capacity ratios, a first capacity ratio associated with at least one first memory die of the plurality of memory dies is less than a second capacity ratio associated with at least one second memory die of the plurality of memory dies.
Other embodiments are possible, and each of the embodiments can be used alone or together in combination. Accordingly, various embodiments will now be described with reference to the attached drawings.